Specifications
ispLSI and pLSI 1032
Internal Timing Parameters
1
2
PARAMETER
#
DESCRIPTION
-90
-80
-60
UNITS
Outputs
t
ob
t
oen
t
odis
Clocks
t
gy0
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
USE 1032E-8
FOR NEW DE 0
SIGNS
USE 1032E-7
FOR NEW DE 0
SIGNS
–
–
–
2.4
4.0
4.0
–
–
–
3.0
5.0
5.0
MIN. MAX. MIN. MAX. MIN. MAX.
47
48
49
Output Buffer Delay
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
–
–
–
4.0
6.7
6.7
ns
ns
ns
50
51
52
53
54
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Clock Delay, Clock GLB to Global GLB Clock Line
Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
Clock Delay, Clock GLB to I/O Cell Global Clock Line
3.6
2.8
0.8
2.8
0.8
3.6
4.4
4.0
4.4
4.0
4.5
3.5
1.0
3.5
1.0
4.5
5.5
5.0
5.5
5.0
6.0
4.6
1.3
4.6
1.3
6.0
7.3
6.6
7.3
6.6
ns
ns
ns
ns
ns
Global Reset
t
gr
55
Global Reset to GLB and I/O Registers
–
8.2
–
9.0
–
12.0
ns
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
7
1996 ISP Encyclopedia
LATTICE [ LATTICE SEMICONDUCTOR ]
