Specifications
ispLSI 1032E
Internal Timing Parameters
1
PARAM.
#
DESCRIPTION
-90
-80
-70
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
–
–
–
–
–
1.4
2.4
0.8
0.0
0.8
–
1.7
10.0
5.3
5.3
3.7
1.4
2.9
1.8
0.0
1.8
–
–
–
–
–
2.1
10.0
5.7
5.7
4.3
–
–
–
–
–
2.6
6.2
6.2
5.8
Outputs
52 I/O Cell OE to Output Disabled
53 Global OE
54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
55 Clock Delay, Y1 or Y2 to Global GLB Clock Line
56 Clock Delay, Clock GLB to Global GLB Clock Line
57 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
58 Clock Delay, Clock GLB to I/O Cell Global Clock Line
59 Global Reset to GLB and I/O Registers
ES
IG
1.5
3.1
1.8
0.0
1.8
4.5
1.5
1.5
0.8
0.0
0.8
–
t
ob
t
sl
t
oen
t
odis
t
goe
Clocks
50 Output Buffer Delay, Slew Limited Adder
51 I/O Cell OE to Output Enabled
10.0
N
1.5
1.5
1.8
0.0
1.8
4.6
N
EW
t
gy0
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
t
gr
1.5
2.6
0.8
D
0.0
0.8
–
Global Reset
1. Internal Timing Parameters are not tested and are for reference only.
4.5
R
Table 2-0037B/1032E
U
SE
is
pL
SI
10
32
EA
FO
10
S
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
49 Output Buffer Delay
ns
LATTICE [ LATTICE SEMICONDUCTOR ]
