欢迎访问ic37.com |
会员登录 免费注册
发布采购

ISPLSI1032E100LJ 参数 Datasheet PDF下载

ISPLSI1032E100LJ图片预览
型号: ISPLSI1032E100LJ
PDF下载: 下载PDF文件 查看货源
内容描述: 在系统可编程高密度PLD [In-System Programmable High Density PLD]
分类和应用:
文件页数/大小: 17 页 / 295 K
品牌: LATTICE [ LATTICE SEMICONDUCTOR ]
 浏览型号ISPLSI1032E100LJ的Datasheet PDF文件第4页浏览型号ISPLSI1032E100LJ的Datasheet PDF文件第5页浏览型号ISPLSI1032E100LJ的Datasheet PDF文件第6页浏览型号ISPLSI1032E100LJ的Datasheet PDF文件第7页浏览型号ISPLSI1032E100LJ的Datasheet PDF文件第9页浏览型号ISPLSI1032E100LJ的Datasheet PDF文件第10页浏览型号ISPLSI1032E100LJ的Datasheet PDF文件第11页浏览型号ISPLSI1032E100LJ的Datasheet PDF文件第12页  
Specifications
ispLSI 1032E
Internal Timing Parameters
1
-90
-80
-70
PARAM. #
2
DESCRIPTION
MIN. MAX. MIN. MAX. MIN. MAX.
3.5
0.0
0.3
2.3
5.0
5.0
2.6
2.1
3.5
0.0
0.3
2.7
4.0
0.0
0.3
3.3
UNITS
Inputs
GRP
GLB
is
pL
t
4ptbpc
t
4ptbpr
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
ORP
FO
R
t
grp1
t
grp4
t
grp8
t
grp16
t
grp32
30 GRP Delay, 4 GLB Loads
31 GRP Delay, 8 GLB Loads
32 GRP Delay, 16 GLB Loads
33 GRP Delay, 32 GLB Loads
34 4 Prod.Term Bypass Path Delay (Combinatorial)
35 4 Prod. Term Bypass Path Delay (Registered)
N
EW
29 GRP Delay, 1 GLB Load
D
0.5
7.9
4.5
t
iobp
t
iolat
t
iosu
t
ioh
t
ioco
t
ior
t
din
22 I/O Register Bypass
23 I/O Latch Delay
24 I/O Register Setup Time before Clock
25 I/O Register Hold Time after Clock
26 I/O Register Clock to Out Delay
27 I/O Register Reset to Out Delay
28 Dedicated Input Delay
N
6.1
6.0
2.8
2.5
2.5
3.2
4.0
5.6
8.8
7.2
8.3
8.7
9.2
1.6
2.9
6.8
5.8
9.0
6.2
1.0
0.0
ES
IG
5.4
5.4
2.8
2.2
2.5
2.8
3.5
4.8
7.1
6.7
6.6
7.8
8.2
1.3
2.9
6.4
5.5
8.0
5.8
1.0
0.0
0.5
8.8
4.8
2.3
2.6
3.2
4.4
5.7
6.1
5.6
6.8
7.1
0.4
2.9
6.3
5.1
7.1
5.3
1.0
0.0
0.2
6.8
4.1
37 20 Prod. Term/XOR Path Delay
38 XOR Adjacent Path Delay
3
EA
36 1 Prod.Term/XOR Path Delay
32
39 GLB Register Bypass Delay
40 GLB Register Setup Time before Clock
41 GLB Register Hold Time after Clock
42 GLB Register Clock to Output Delay
43 GLB Register Reset to Output Delay
44 GLB Prod.Term Reset to Register Delay
45 GLB Prod. Term Output Enable to I/O Cell Delay
46 GLB Prod. Term Clock Delay
47 ORP Delay
10
SI
SE
t
orp
t
orpbp
48 ORP Bypass Delay
U
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036B/1032E
8
S
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns