Specifications
ispLSI 1032E
ispLSI 1032E Timing Model
I/O Cell
GRP
Feedback
Ded. In
#34
GRP4
#30
GRP Loading
Delay
#29, 31 - 33
Comb 4 PT Bypass
GLB Reg Bypass
#39
GLB Reg
Delay
D
RST
Reset
#59
#40 - 43
Q
ORP Bypass
#48
ORP
Delay
#47
GLB
ORP
I/O Cell
#28
I/O Reg Bypass
#22
Input
D Register Q
RST
#23 - 27
#35
20 PT
XOR Delays
#36 - 38
#59
D
R
N
EW
Table 2-0042a/1032E
Clock
Distribution
Y1,2,3
#55 - 58
Control RE
PTs
OE
#44 - 46 CK
Y0
GOE 0,1
#54
#53
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
t
h
t
co
t
su
=
=
=
2.9 ns =
SE
t
h
=
=
=
2.7 ns =
=
=
=
5.5 ns =
U
t
co
1. Calculations are based upon timing specifications for the ispLSI 1032E-125.
is
pL
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) – (
t
gy0(min) +
t
gco +
t
gcp(min))
(#22 + #30 + #37) + (#40) – (#54 + #42 + #56)
(0.3 + 2.0 + 5.0) + (0.1) – (1.4 + 2.3 + 0.8)
Clock (max) + Reg h - Logic
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gh) – (
t
iobp +
t
grp4 +
t
20ptxor)
(#54 + #42 + #56) + (#41) – (#22 + #30 + #37)
(1.4 + 2.3 + 1.8) + (4.5) – (0.3 + 2.0 + 5.0)
Clock (max) + Reg co + Output
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gco) + (
t
orp +
t
ob)
(#54 + #42 + #56) + (#42) + (#47 + #49)
(1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3)
SI
=
=
=
10.9 ns =
Clock (max) + Reg co + Output
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#22 + #30 + #46) + (#42) + (#47 + #49)
(0.3 + 2.0 + 4.0) + (2.3) + (1.0 + 1.3)
10
32
=
=
=
3.5 ns =
Clock (max) + Reg h - Logic
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gh) – (
t
iobp +
t
grp4 +
t
20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 2.0 + 4.0) + (4.5) – (0.3 + 2.0 + 5.0)
EA
FO
t
su
=
=
=
2.2 ns =
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) – (
t
iobp +
t
grp4 +
t
ptck(min))
(#22 + #30 + #37) + (#40) – (#22 + #30 + #46)
(0.3 + 2.0 + 5.0) + (0.1) – (0.3 + 2.0 + 2.9)
11
ES
IG
0491
N
#51, 52
S
I/O Pin
(Input)
Reg 4 PT Bypass
#49, 50
I/O Pin
(Output)
LATTICE [ LATTICE SEMICONDUCTOR ]
