Specifications
ispLSI 1032E
Maximum GRP Delay vs GLB Loads
6.0
ispLSI 1032E-70
GRP Delay (ns)
5.0
4.0
ispLSI 1032E-80
ispLSI 1032E-90/100
ispLSI 1032E-125
3.0
2.0
1.0
GLB Load
Power Consumption
Power consumption in the ispLSI 1032E device depends
on two primary factors: the speed at which the device is
operating, and the number of product terms used. Figure
Figure 3. Typical Device Power Consumption vs fmax
350
300
32
EA
I
CC (mA)
200
150
is
pL
SI
100
10
250
0
20
40
FO
ispLSI 1032E
R
3 shows the relationship between power and operating
speed.
60
80
f
max (MHz)
100
I
CC
can be estimated for the ispLSI 1032E using the following equation:
U
I
CC
(mA) = 15 + (# of PTs * 0.59) + (# of nets * Max freq * 0.0078)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I
CC
estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of I
CC
is sensitive to operating
conditions and the program in the device, the actual I
CC
should be verified.
SE
Notes: Configuration of eight 16-bit counters
Typical current at 5V, 25°C
N
EW
1
4
8
16
32
GRP/GLB/1032E
125
D
0127/1032E
12
ES
IG
N
S
LATTICE [ LATTICE SEMICONDUCTOR ]
