88F6180
Hardware Specifications
1.2.2
Table 4:
Miscellaneous Pin Assignment
The Miscellaneous signal list contains clock and reset, test, and related signals.
Miscellaneous Pin Assignments
I /O
Pi n
Ty pe
Analog
P ow e r
Rail
XTAL_AVDD
D e s c r i p t io n
Pin Name
REF_CLK_XIN
I
Reference clock input from external oscillator or input from
external crystal. Used as input to core, CPU, and USB PLLs.
XTAL_OUT
Feedback signal to external crystal.
When not used, leave this pin floating.
System reset
Main reset signal of the device clock. Used to reset all units
to their initial state.
When in the reset state, most output pins are in Tri-State.
Reset request from the device to the board reset logic.
This pin is multiplexed on the MPP pins (see
Optional PCI Express Endpoint card reset output
This pin is multiplexed on the MPP pins (see
Analog Test Point for USB, and PCI Express interfaces
For internal use. Leave this pin unconnected.
USB_ISET (output): Current Reference
Pull down to VSS through a 6.04 k
Ω
pull-down resistor. See
the
88F6180, 88F6190, 88F6192, and 88F6281 Design
Guide
for the recommended resistor value.
XOUT
O
Analog
XTAL_AVDD
SYSRSTn
I
CMOS
VDDO
SYSRST_OUTn
O
CMOS
VDDO
PEX_RST_OUTn
O
CMOS
VDDO
TP
O
Analog
ISET
I
Analog
MRn
I
CMOS
VDD_GE
Active-Low, Manual Reset Input
SYSRST_OUTn is asserted low as long as the MRn input
signal is asserted low, and for additional 20 ms after MRn
(manual reset) de-assertion
This pin is internally pulled up.
Reserved for Marvell
®
future usage.
Leave unconnected externally.
NC
Doc. No. MV-S104988-U0 Rev. E
Page 20
Document Classification: Proprietary Information
Copyright © 2008 Marvell
December 2, 2008, Preliminary
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
