Pin and Signal Descriptions
Pin Descriptions
1.2.4
Table 6:
PCI Express Interface Pin Assignments
PCI Express Interface Pin Assignments
I/O
P in
Ty p e
HCSL
Power
R a il
PEX_AVDD
D e s c r i p t io n
Pin Name
PEX_CLK_P/N
I/O
PCI Express Reference Clock
100 MHz, differential
This clock can be configured as input or output according to the
reset strap (see
NOTE:
For Output mode, 50-ohm, pull-down resistors are
required.
Transmit Lane
Differential pair of PCI Express transmit data
Receive Lane
Differential pair of PCI Express receive data
Current reference. Pull down to VSS through a 5 k
Ω
resistor.
See the
88F6180, 88F6190, 88F6192, and 88F6281 Design
Guide
for the recommended resistor value.
PEX_TX_P/N
O
CML
PEX_AVDD
PEX_RX_P/N
I
CML
PEX_AVDD
PEX_ISET
I
Analog
Copyright © 2008 Marvell
December 2, 2008, Preliminary
Document Classification: Proprietary Information
Doc. No. MV-S104988-U0 Rev. E
Page 23
MARVELL [ MARVELL TECHNOLOGY GROUP LTD. ]
