512Mb, 1Gb, 2Gb: P30-65nm
Status Register
Status Register
Read Status Register
To read the status register, issue the READ STATUS REGISTER command at any address.
Status register information is available at the address that the READ STATUS REGISTER,
WORD PROGRAM, or BLOCK ERASE command is issued to. Status register data is auto-
matically made available following a word program, block erase, or block lock com-
mand sequence. Reads from the device after any of these command sequences will out-
put the devices status until another valid command is written (e.g. READ ARRAY com-
mand).
The status register is read using single asynchronous mode or synchronous burst mode
reads. Status register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. In
asynchronous mode, the falling edge of OE# or CE# (whichever occurs first) updates
and latches the status register contents. However, when reading the status register in
synchronous burst mode, CE# or ADV# must be toggled to update status data.
The device write status bit (SR7) provides the overall status of the device. SR[6:1]
present status and error information about the PROGRAM, ERASE, SUSPEND, V
PP
, and
BLOCK LOCK operations.
Note:
Reading the status register is a nonarray READ operation. When the operation oc-
curs in asynchronous page mode, only the first data is valid and all subsequent data are
undefined. When the operation occurs in synchronous burst mode, the same data word
requested will be output on successive clock edges until the burst length requirements
are satisfied.
Table 12: Status Register Description
Notes apply to entire table
Bits Name
7
6
5:4
Device write status
(DWS)
Erase Suspend Status
(ESS)
Erase/Blank check status
(ES)
Program status (PS)
V
PP
status (VPPS)
Program suspend status
(PSS)
Block lock status (BLS)
BEFP status (BWS)
Notes:
Bit Settings
0 = Busy
1 = Ready
0 = Not in effect
1 = In effect
00 = PROGRAM/ERASE successful
01 = PROGRAM error
10 = ERASE/BLANK CHECK error
11 = Command sequence error
0 = Within limits
1 = Exceeded limits (V
PP
≤
V
PPLK
)
0 = Not in effect
1 = In effect
0 = Not locked
1 = Locked (operation aborted)
0 = BEFP complete
1 = BEFP in progress
Description
Status bit:
Indicates whether a PROGRAM or
ERASE command cycle is in progress.
Status bit:
Indicates whether an ERASE operation
has been or is going to be suspended.
Status/Error bit:
Indicates whether an ERASE/
BLANK CHECK or PROGRAM operation was success-
ful. When an error is returned, the operation is
aborted.
Status bit:
Indicates whether a PROGRAM/ERASE
operation is within acceptable voltage range limits.
Status bit:
Indicates whether a PROGRAM opera-
tion has been or is going to be suspended.
Status bit:
Indicates whether a block is locked
when a PROGRAM or ERASE operation is initiated.
Status bit:
Indicates whether BEFP data has com-
pleted loading into the buffer.
3
2
1
0
1. Default value = 0x80.
2. Always clear the status register prior to resuming ERASE operations. This eliminates sta-
tus register ambiguity when issuing commands during ERASE SUSPEND. If a command
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
37
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