512Mb, 1Gb, 2Gb: P30-65nm
Configuration Register
Latency Count
The latency count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven to DQ[15:0]. The input clock frequency is used to deter-
mine this value. The First Access Latency Count figure shows the data output latency for
different LC settings.
Figure 10: First Access Latency Count
CLK [C]
Address [A]
Valid
Address
ADV# [V]
Code
DQ[15:0] [D/Q]
0 (Reserved
Valid
Output
Code 1
(Reserved )
Code
DQ[15:0] [D/Q]
2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ[15:0] [D/Q]
(Reserved )
DQ[15:0] [D/Q]
Code
3
DQ[15:0] [D/Q]
Code
4
DQ[15:0] [D/Q]
Code
5
DQ[15:0] [D/Q]
Code
6
DQ[15:0] [D/Q]
Code
7
Note:
1. First Access Latency Count Calculation:
• 1 / CLK frequency = CLK period (ns)
• n x (CLK period)
≥
t
AVQV (ns) –
t
CHQV (ns)
• Latency Count = n
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
40
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