512Mb, 1Gb, 2Gb: P30-65nm
Configuration Register
Figure 11: Example Latency Count Setting Using Code 3
0
CLK
1
2
3
tData
4
CE#
ADV#
A[MAX:1]
Code 3
D[15:0]
High-Z
Address
Data
R103
End of Wordline Considerations
End of wordline (EOWL) wait states can result when the starting address of the burst op-
eration is not aligned to a 16-word boundary; that is, A[4:1] of the start address does not
equal 0x0. The figure below illustrates the end of wordline wait state(s) that occur after
the first 16-word boundary is reached. The number of data words and wait states is
summarized in the table below.
Figure 12: End of Wordline Timing Diagram
Latency Count
CLK
A[MAX:1]
Address
DQ[15:0]
ADV#
OE#
WAIT#
Data
Data
Data
EOWL
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
41
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