512Mb, 1Gb, 2Gb: P30-65nm
One-Time Programmable Registers
One-Time Programmable Registers
Read OTP Registers
The device contains 17 OTP registers that can be used to implement system security
measures and/or device identification. Each OTP register can be individually locked.
The first 128-bit OTP register is comprised of two 64-bit (8-word) segments. The lower
64-bit segment is preprogrammed at the Micron factory with a unique 64-bit number.
The upper 64-bit segment, as well as the other sixteen 128-bit OTP registers, are blank.
Users can program them as needed. Once programmed, users can also lock the OTP
register(s) to prevent additional bit programming (see the OTP Register Map figure be-
low).
The OTP registers contain OTP bits; when programmed, PR bits cannot be erased. Each
OTP register can be accessed multiple times to program individual bits, as long as the
register remains unlocked.
Each OTP register has an associated lock register bit. When a lock register bit is pro-
grammed, the associated OTP register can only be read; it can no longer be program-
med. Additionally, because the lock register bits themselves are OTP, when program-
med, they cannot be erased. Therefore, when an OTP register is locked, it cannot be un-
locked.
The OTP registers can be read from an OTP-RA address. To read the OTP register, a
READ DEVICE IDENTIFIER command is issued at an OTP-RA address to place the de-
vice in the read device identifier state. Next, a READ operation is performed using the
address offset corresponding to the register to be read. The Device Identifier Informa-
tion table shows the address offsets of the OTP registers and lock registers. PR data is
read 16 bits at a time.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
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