512Mb, 1Gb, 2Gb: P30-65nm
Configuration Register
Table 16: Burst Sequence Word Ordering (Continued)
Burst Addressing Sequence (DEC)
Start
Address
(DEC)
4
5
6
7
⋮
14
15
Burst
Wrap
(RCR3)
1
1
1
1
⋮
1
1
⋮
4-Word Burst
(BL[2:0] =
0b001)
8-Word Burst
(BL[2:0] = 0b010)
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
⋮
16-Word Burst
(BL[2:0] = 0b011)
4-5-6-7-8…18-19
5-6-7-8-9…19-20
6-7-8-9-10…20-21
7-8-9-10-11…21-22
⋮
14-15-16-17-18…28-29
15-16-17-18-19…29-30
Continuous Burst
(BL[2:0] = 0b111)
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
⋮
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
Clock Edge
The clock edge (CE) bit selects either a rising (default) or falling clock edge for CLK. This
clock edge is used at the start of a burst cycle to output synchronous data and to
assert/de-assert WAIT.
Burst Wrap
The burst wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length
accesses wrap within the selected word length boundaries or cross word length boun-
daries. When BW is set, burst wrapping does not occur (default). When BW is cleared,
burst wrapping occurs.
When performing synchronous burst reads with BW set (no wrap), an output delay may
occur when the burst sequence crosses its first device row (16-word) boundary. If the
burst sequence’s start address is 4-word aligned, then no delay occurs. If the start ad-
dress is at the end of a 4-word boundary, the worst-case output delay is one clock cycle
less than the first access latency count. This delay can take place only once and doesn’t
occur if the burst sequence does not cross a device row boundary. WAIT informs the
system of this delay when it occurs.
Burst Length
The burst length bits (BL[2:0]) select the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, or con-
tinuous.
Continuous burst accesses are linear only and do not wrap within any word length
boundaries. When a burst cycle begins, the device outputs synchronous burst data until
it reaches the end of the “burstable” address space.
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
44
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