512Mb, 1Gb, 2Gb: P30-65nm
Configuration Register
Table 15: WAIT Functionality Table (Continued)
Condition
All Writes
Notes:
WAIT
High-Z
1. Active means that WAIT is asserted until data becomes valid, then deasserts.
2. When OE# = V
IH
during writes, WAIT = High-Z.
Notes
WAIT Delay
The WAIT delay (WD) bit controls the WAIT assertion delay behavior during synchro-
nous burst reads. WAIT can be asserted either during or one data cycle before valid data
is output on DQ[15:0]. When WD is set, WAIT is de-asserted one data cycle
before
valid
data (default). When WD is cleared, WAIT is de-asserted
during
valid data.
Burst Sequence
The burst sequence (BS) bit selects linear burst sequence (default). Only linear burst se-
quence is supported. The synchronous burst sequence for all burst lengths, as well as
the effect of the burst wrap (BW) setting are shown below.
Table 16: Burst Sequence Word Ordering
Burst Addressing Sequence (DEC)
Start
Address
(DEC)
0
1
2
3
4
5
6
7
⋮
14
15
⋮
0
1
2
3
Burst
Wrap
(RCR3)
0
0
0
0
0
0
0
0
⋮
0
0
⋮
1
1
1
1
⋮
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
⋮
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
3-4-5-6-7-8-9-10
⋮
4-Word Burst
(BL[2:0] =
0b001)
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
8-Word Burst
(BL[2:0] = 0b010)
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
⋮
16-Word Burst
(BL[2:0] = 0b011)
0-1-2-3-4…14-15
1-2-3-4-5…15-0
2-3-4-5-6…15-0-1
3-4-5-6-7…15-0-1-2
4-5-6-7-8…15-0-1-2-3
5-6-7-8-9…15-0-1-2-3-4
6-7-8-9-10…15-0-1-2-3-4-5
7-8-9-10…15-0-1-2-3-4-5-6
⋮
14-15-0-1-2…12-13
15-0-1-2-3…13-14
⋮
0-1-2-3-4…14-15
1-2-3-4-5…15-16
2-3-4-5-6…16-17
3-4-5-6-7…17-18
Continuous Burst
(BL[2:0] = 0b111)
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
⋮
14-15-16-17-18-19-20-…
15-16-17-18-19-20-21-…
⋮
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
PDF: 09005aef845667b3
p30_65nm_MLC_512Mb-1gb_2gb.pdf - Rev. B 12/13 EN
43
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