Micron M25P40 Serial Flash Embedded Memory
Operating Features
Operating Features
Page Programming
To program one data byte, two commands are required: WRITE ENABLE, which is one
byte, and a PAGE PROGRAM sequence, which is four bytes plus data. This is followed by
the internal PROGRAM cycle of duration t
PP
. To spread this overhead, the PAGE PRO-
GRAM command allows up to 256 bytes to be programmed at a time (changing bits
from 1 to 0), provided they lie in consecutive addresses on the same page of memory. To
optimize timings, it is recommended to use the PAGE PROGRAM command to program
all consecutive targeted bytes in a single sequence than to use several PAGE PROGRAM
sequences with each containing only a few bytes.
Sector Erase, Bulk Erase
The PAGE PROGRAM command allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be ach-
ieved a sector at a time using the SECTOR ERASE command, or throughout the entire
memory using the BULK ERASE command. This starts an internal ERASE cycle of dura-
tion t
SSE
, t
SE
or t
BE
. The ERASE command must be preceded by a WRITE ENABLE com-
mand.
Polling during a Write, Program, or Erase Cycle
An improvement in the time to complete the following commands can be achieved by
not waiting for the worst case delay (t
W
, t
PP
, t
SE
, or t
BE
).
• WRITE STATUS REGISTER
• PROGRAM
• ERASE (SECTOR ERASE, BULK ERASE)
The write in progress (WIP) bit is provided in the status register so that the application
program can monitor this bit in the status register, polling it to establish when the pre-
vious WRITE cycle, PROGRAM cycle, or ERASE cycle is complete.
Active Power, Standby Power, and Deep Power-Down
When chip select (S#) is LOW, the device is selected, and in the ACTIVE POWER mode.
When S# is HIGH, the device is deselected, but could remain in the ACTIVE POWER
mode until all internal cycles have completed (PROGRAM, ERASE, WRITE STATUS
REGISTER). The device then goes in to the STANDBY POWER mode. The device con-
sumption drops to I
CC1
.
The DEEP POWER-DOWN mode is entered when the DEEP POWER-DOWN command
is executed. The device consumption drops further to I
CC2
. The device remains in this
mode until the RELEASE FROM DEEP POWER-DOWN command is executed. While in
the DEEP POWER-DOWN mode, the device ignores all WRITE, PROGRAM, and ERASE
commands. This provides an extra software protection mechanism when the device is
not in active use, by protecting the device from inadvertent WRITE, PROGRAM, or
ERASE operations. For further information, see the DEEP POWER DOWN command.
PDF: 09005aef8456654f
m25p40.pdf - Rev. Y 8/12 EN
11
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2011 Micron Technology, Inc. All rights reserved.
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