ADVANCE
512Mb: x4, x8, x16
DDR SDRAM
512Mb DDR SDRAM PART NUMBERS
(Note: xx= -75, -75Z, or -8)
PART NUMBER
MT46V128M4TG-xx
MT46V128M4TG-xxL
MT46V64M8TG-xx
MT46V64M8TG-xxL
MT46V32M16TG-xx
MT46V32M16TG-xxL
CONFIGURATION
128 Meg x 4
128 Meg x 4
64 Meg x 8
64 Meg x 8
32 Meg x 16
32 Meg x 16
I/O DRIVE LEVEL
Full Drive
Full Drive
Full Drive
Full Drive
Programmable Drive
Programmable Drive
REFRESH OPTION
Standard
Low Power
Standard
Low Power
Standard
Low Power
GENERAL DESCRIPTION
The 512Mb DDR SDRAM is a high-speed CMOS,
dynamic random-access memory containing
536,870,912 bits. It is internally configured as a quad-
bank DRAM.
The 512Mb DDR SDRAM uses a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the 512Mb DDR SDRAM
effectively consists of a single 2n-bit wide, one-clock-
cycle data transfer at the internal DRAM core and two
corresponding
n-bit
wide, one-half-clock-cycle data
transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted ex-
ternally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR
SDRAM during READs and by the memory controller
during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs. The
x16 offering has two data strobes, one for the lower byte
and one for the upper byte.
The 512Mb DDR SDRAM operates from a differen-
tial clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to the DDR SDRAM are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the bank and row to be accessed. The address
bits registered coincident with the READ or WRITE com-
mand are used to select the bank and the starting col-
umn location for the burst access.
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a self-
timed row precharge that is initiated at the end of the
burst access.
As with standard SDR SDRAMs, the pipelined,
multibank architecture of DDR SDRAMs allows for con-
current operation, thereby providing high effective
bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All full
drive strength outputs are SSTL_2, Class II compat-
ible.
NOTE:
1. The functionality and the timing specifications
discussed in this data sheet are for the DLL-enabled
mode of operation.
2. Throughout the data sheet, the various figures and
text refer to DQs as “DQ.” The DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise. Additionally, the x16 is
divided in to two bytes—the lower byte and upper
byte. For the lower byte (DQ0 through DQ7) DM
refers to LDM and DQS refers to LDQS; and for the
upper byte (DQ8 through DQ15) DM refers to UDM
and DQS refers to UDQS.
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
MICRON [ MICRON TECHNOLOGY ]
