PRELIMINARY
1Gb: x4, x8, x16
DDR SDRAM
Figure 17: READ to PRECHARGE
T0
CK#
CK
COMMAND
6
ADDRESS
READ
Bank
a,
Col
n
NOP
PRE
Bank
a,
(a or
all)
NOP
NOP
ACT
Bank
a,
Row
T1
T2
T2n
T3
T3n
T4
T5
CL = 2
DQS
DQ
T0
CK#
CK
COMMAND
6
ADDRESS
READ
Bank
a,
Col
n
NOP
PRE
Bank
a,
(a or
all)
NOP
DO
n
tRP
T1
T2
T2n
T3
T3n
T4
T5
NOP
ACT
Bank
a,
Row
CL = 2.5
DQS
DQ
DO
n
tRP
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DO
n
= data-out from column
n.
Burst length = 4, or an interrupted burst of 8.
Three subsequent elements of data-out appear in the programmed order following DO
n.
Shown with nominal
t
AC,
t
DQSCK, and
t
DQSQ.
READ to PRECHARGE equals two clocks, which allows two data pairs of data-out.
A READ command with AUTO-PRECHARGE enabled, provided
t
RAS(min) is met, would cause a precharge to be performed at
x
number of clock cycles after the READ command, where
x
= BL / 2.
7. PRE = PRECHARGE command; ACT = ACTIVE command.
2.
3.
4.
5.
6.
09005aef8076894f
1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
