128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Power and Reset Specifications
Power and Reset Specifications
Initialization
Proper device initialization and operation is dependent on the power-up/down se-
quence, reset procedure, and adequate power-supply decoupling.
Power-Up and Down
To avoid conditions that may result in spurious PROGRAM or ERASE operations, the
power sequences shown below are recommended. Note that each power supply must
be at its minimum voltage range before applying or removing the next supply voltage in
the sequence. Also, device inputs must not be driven until all supply voltages have at-
tained their minimum range, and RST# should be LOW during all power transitions.
When powering down the device, voltages should reach 0V before power is reapplied to
ensure proper device initialization. Otherwise, indeterminate operation could result.
When V
CCQ
goes below V
LKOQ
, the device is reset.
Table 31: Power Sequencing
Power Supply
V
CC,min
V
CCQ,min
V
PP,min
First
Second
Third
Note:
Power-Up Sequence
First
Second
1
Second
1
First
1
First
1
Second
First
1
Second
First
1
Third
Second
First
Power-Down Sequence
Second
First
1
First
1
Second
1
Second
1
First
Second
1
First
Second
1
1. Connected/sequenced together.
Reset
During power-up and power-down, RST# should be asserted to prevent spurious PRO-
GRAM or ERASE operations. While RST# is LOW, device operations are disabled, all in-
puts such as address and control are ignored, and all outputs such as data and WAIT are
placed in High-Z. Invalid bus conditions are effectively masked out.
Upon power-up, RST# can be de-asserted after
t
VCCPH, allowing the device to exit from
reset. Upon exiting from reset, the device defaults to asynchronous read array mode,
and the status register defaults to 0080h. Array data is available after
t
PHQV, or a bus
WRITE cycle can begin after
t
PHWL. If RST# is asserted during a PROGRAM or ERASE
operation, the operation will abort and array contents at that location will be invalid.
For proper system initialization, connect RST# to the LOW true reset signal that asserts
whenever the processor is reset. This will ensure the device is in the expected read
mode (read array) upon startup.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
53
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2011 Micron Technology, Inc. All rights reserved.
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