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PF48F4000P0ZB 参数 Datasheet PDF下载

PF48F4000P0ZB图片预览
型号: PF48F4000P0ZB
PDF下载: 下载PDF文件 查看货源
内容描述: 美光并行NOR闪存的嵌入式存储器( P30-65nm ) [Micron Parallel NOR Flash Embedded Memory (P30-65nm)]
分类和应用: 闪存存储
文件页数/大小: 98 页 / 1366 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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256Mb and 512Mb (256Mb/256Mb), P30-65nm  
Program Operations  
the maximum buffer size of 512 words. During the buffer-loading sequence, data is stor-  
ed to sequential buffer locations starting at address 0x00. Programming of the buffer  
contents to the array starts as soon as the buffer is full. If the number of words is less  
than 512, the remaining buffer locations must be filled with 0xFFFF.  
Note: The buffer must be completely filled for programming to occur. Supplying an ad-  
dress outside of the current block's range during a buffer-fill sequence causes the algo-  
rithm to exit immediately. Any data previously loaded into the buffer during the fill cy-  
cle is not programmed into the array.  
The starting address for data entry must be buffer size aligned; if not, the BEFP algo-  
rithm will be aborted, the program fails, and the (SR4) flag will be set.  
Data words from the write buffer are directed to sequential memory locations in the ar-  
ray; programming continues from where the previous buffer sequence ended. The host  
programming system must poll SR0 to determine when the buffer program sequence  
completes. SR0 cleared indicates that all buffer data has been transferred to the array;  
SR0 set indicates that the buffer is not available yet for the next fill cycle. The host sys-  
tem may check full status for errors at any time, but it is only necessary on a block basis  
after BEFP exit. After the buffer fill cycle, no WRITE cycles should be issued to the de-  
vice until SR0 = 0 and the device is ready for the next buffer fill.  
Note: Any spurious writes are ignored after a BUFFER FILL operation and when internal  
program is proceeding.  
The host programming system continues the BEFP algorithm by providing the next  
group of data words to be written to the buffer. Alternatively, it can terminate this phase  
by changing the block address to one outside of the current block’s range.  
The program/verify phase concludes when the programmer writes to a different block  
address; data supplied must be 0xFFFF. Upon program/verify phase completion, the de-  
vice enters the BEFP exit phase.  
Program Suspend  
Issuing the PROGRAM SUSPEND command while programming suspends the pro-  
gramming operation. This allows data to be accessed from the device other than the  
one being programmed. The PROGRAM SUSPEND command can be issued to any de-  
vice address. A PROGRAM operation can be suspended to perform reads only. Addition-  
ally, a PROGRAM operation that is running during an erase suspend can be suspended  
to perform a READ operation.  
When a programming operation is executing, issuing the PROGRAM SUSPEND com-  
mand requests the device to suspend the programming algorithm at predetermined  
points. The device continues to output status register data after the PROGRAM SUS-  
PEND command is issued. Programming is suspended when SR[7,2] are set.  
To read data from the device, the READ ARRAY command must be issued. READ ARRAY,  
READ STATUS REGISTER, READ DEVICE IDENTIFIER, READ CFI, and PROGRAM RE-  
SUME valid commands during a program suspend.  
During a program suspend, de-asserting CE# places the device in standby, reducing ac-  
tive current. VPP must remain at its programming level, and WP# must remain un-  
changed while in program suspend. If RST# is asserted, the device is reset.  
PDF: 09005aef84566799  
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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