256Mb and 512Mb (256Mb/256Mb), P30-65nm
Erase Operations
BLANK CHECK operation progress and errors are determined by reading the status reg-
ister at any address within the block being accessed. SR7 = 0 is a BLANK CHECK busy
status. SR7 = 1 is a BLANK CHECK operation complete status. The status register should
be checked for any errors and then cleared. If the BLANK CHECK operation fails, mean-
ing the block is not completely erased, SR5 = 1. CE# or OE# toggle (during polling) up-
dates the status register.
The READ STATUS REGISTER command must always be followed by a CLEAR STATUS
REGISTER command. The device remains in status register mode until another com-
mand is written to the device. Any command can follow once the BLANK CHECK com-
mand is complete.
ERASE SUSPEND Command
The ERASE SUSPEND command suspends a BLOCK ERASE operation that is in pro-
gress, enabling access to data in memory locations other than the one being erased. The
ERASE SUSPEND command can be issued to any device address. A BLOCK ERASE oper-
ation can be suspended to perform a WORD or BUFFER PROGRAM operation, or a
READ operation within any block except the block that is erase suspended.
When a BLOCK ERASE operation is executing, issuing the ERASE SUSPEND command
requests the device to suspend the erase algorithm at predetermined points. The device
continues to output status register data after the ERASE SUSPEND command is issued.
Block erase is suspended when SR[7,6] are set.
To read data from the device (other than an erase-suspended block), the READ ARRAY
command must be issued. During erase suspend, a PROGRAM command can be issued
to any block other than the erase-suspended block. Block erase cannot resume until
program operations initiated during erase suspend complete. READ ARRAY, READ STA-
TUS REGISTER, READ DEVICE IDENTIFIER, READ CFI, and ERASE RESUME are valid
commands during erase suspend. Additionally, CLEAR STATUS REGISTER, PROGRAM,
PROGRAM SUSPEND, BLOCK LOCK, BLOCK UNLOCK, and BLOCK LOCK DOWN are
valid commands during an ERASE SUSPEND operation.
During an erase suspend, de-asserting CE# places the device in standby, reducing active
current. VPP must remain at a valid level, and WP# must remain unchanged while in
erase suspend. If RST# is asserted, the device is reset.
ERASE RESUME Command
The ERASE RESUME command instructs the device to continue erasing, and automati-
cally clears SR[7,6]. This command can be written to any address. If status register error
bits are set, the status register should be cleared before issuing the next instruction.
RST# must remain de-asserted.
Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If
VPP is at or below VPPLK, ERASE operations halt and SR3 is set indicating a VPP-level er-
ror.
PDF: 09005aef84566799
p30_65nm_MLC_256Mb-512mb.pdf - Rev. C 12/13 EN
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