64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Bus Operating Modes
Figure 12:
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
Additional WAIT states inserted to allow refresh completion.
D[0]
D[1]
D[2]
D[3]
DON’T CARE
High-Z
VALID
ADDRESS
Refresh Collision During WRITE Operation
CLK
A[21:0]
ADV#
CE#
OE#
WE#
LB#/UB#
WAIT
DQ[15:0]
Note:
Non-default BCR settings for refresh collision during WRITE operation: Latency code two
(three clocks); WAIT active LOW; WAIT asserted during delay.
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
15
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©2003 Micron Technology, Inc. All rights reserved.
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