64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Figure 20:
CLK
WAIT
WAIT
BCR[8] = 0
Data valid in current cycle.
BCR[8] = 1
Data valid in next cycle.
WAIT Configuration During Burst Operation
DQ[15:0]
D[0]
D[1]
D[2]
D[3]
D[4]
DON’T CARE
Note:
Non-default BCR setting for WAIT configuration during burst operation: WAIT active LOW.
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or
LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserted state.
Latency Counter (BCR[13:11]) Default = Three-Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a
READ or WRITE operation and the first data value transferred. Only latency code two
(three clocks) or latency code three (four clocks) is allowed (see Table 5 and Figure 21)
Table 5:
Latency Configuration
Max Input CLK Frequency (MHz)
Latency Configuration Code
2 (3 clocks)
3 (4 clocks) – default
-708
53 (18.75ns)
80 (12.50ns)
-706/-856
44
1
(22.7ns)
66 (15.20ns)
Notes: 1. Clock rates below 50 MHz are allowed as long as
t
CSP specifications are met.
Figure 21:
Latency Counter
CLK
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
VALID
ADDRESS
A[21:0]
ADV#
Code 2
DQ[15:0]
V
OH
V
OL
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Code 3
DQ[15:0]
V
OH
V
OL
(Default)
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
DON’T CARE
UNDEFINED
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
MICROTUNE [ MICROTUNE,INC ]
