64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus.
Page mode operation is enabled by a bit contained in the RCR. Figure 17 describes the
control bits in the BCR. At power-up, the BCR is set to 9D4Fh.
The BCR is accessed using CRE and A[19] HIGH, or through the configuration register
software sequence with DQ = 0001h on the third cycle.
Figure 17:
Bus Configuration Register Definition
A[21:20] A19 A[18:16]
A15
A14 A13 A12A11 A10
A9
A8
A7
A6
A5
A4
A3
A2 A1 A0
21–20
Reserved
19
Register
Select
18–16
Reserved
15
Operating
Mode
14
Reserved
13 12 11
Latency
Counter
10
WAIT
Polarity
9
Reserved
8
WAIT
Configuration (WC)
7
Reserved
6
Clock
Configuration (CC)
5
Output
Impedance
4
Reserved
3
2
1
0
Burst
Burst
Wrap (BW)* Length (BL)*
All must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
Must be set to "0"
BCR[13] BCR[12] BCR[11]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Latency Counter
Code 0–Reserved
Code 1–Reserved
Code 2
Code 3 (Default)
Code 4–Reserved
Code 5–Reserved
Code 6–Reserved
Code 7–Reserved
BCR[3]
0
1
Burst Wrap (Note 1)
Burst wraps within the burst length
Burst no wrap (default)
BCR[10]
0
1
Active LOW
WAIT Polarity
Active HIGH (default)
BCR[5]
0
1
Output Impedance
Full Drive (default)
1/4 Drive
BCR[8]
0
1
WAIT Configuration
Asserted during delay
Asserted one data cycle before delay (default)
BCR[6]
0
1
Clock Configuration
Not supported
Rising edge (default)
BCR[15]
0
1
Operation Mode
Synchronous burst access mode
Asynchronous access mode (default)
BCR[2]
0
0
BCR[1] BCR[0]
0
1
1
1
1
0
1
1
Burst Length (Note 1)
4 words
8 words
16 words
Continuous burst (default)
BCR[19]
0
1
Select RCR
Select BCR
Register Select
0
1
Note:
All burst WRITEs are continuous.
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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