64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Electrical Characteristics
Table 14: Asynchronous READ Cycle Timing Requirements
-70x
Max
-856
Max
Parameter1
Symbol
Min
Min
Units Notes
70
70
20
85
85
25
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
ADV# Access Time
tAADV
tAPA
tAVH
tAVS
tBA
Page Access Time
5
5
Address Hold from ADV# HIGH
Address Setup to ADV# HIGH
LB#/UB# Access Time
10
10
70
8
85
8
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
3
2
LB#/UB# Disable to DQ High-Z Output
LB#/UB# Enable to Low-Z Output
Maximum CE# Pulse Width
CE# LOW to WAIT Valid
tBHZ
tBLZ
tCEM
tCEW
tCO
10
1
10
1
8
8
7.5
70
7.5
85
Chip Select Access Time
tCVS
tHZ
10
10
5
10
10
5
CE# LOW to ADV# HIGH
8
20
8
8
20
8
4
3
Chip Disable to DQ and WAIT High-Z Output
Chip Enable to Low-Z Output
Output Enable to Valid Output
Output Hold from Address Change
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Page Cycle Time
tLZ
tOE
tOH
tOHZ
tOLZ
tPC
4
3
5
5
20
70
10
10
25
85
10
10
READ Cycle Time
tRC
ADV# Pulse Width LOW
tVP
ADV# Pulse Width HIGH
tVPH
Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. Page-mode enabled only.
3. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The
Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward
either VOH or VOL.
4. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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