64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Electrical Characteristics
Table 15: Burst READ Cycle Timing Requirements
-708
-706/-856
Parameter1
Symbol
Min
Max
Min
Max
Units
Notes
tABA
tACLK
tBOE
46.5
9
56
11
20
ns
ns
ns
ns
Burst to READ Access Time
CLK to Output Delay
20
Burst OE# LOW to Output Delay
CE# HIGH between Subsequent Mixed-Mode tCBPH
Operations
5
5
2
2
tCEM
tCEW
tCLK
tCSP
tHD
8
8
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Maximum CE# Pulse Width
CE# LOW to WAIT Valid
CLK Period
1
12.5
4.5
2
7.5
20
20
1
15
5
7.5
20
20
3
4
CE# Setup Time to Active CLK Edge
Hold Time from Active CLK Edge
Chip Disable to DQ and WAIT High-Z Output tHZ
2
8
1.8
9
8
2.0
11
8
CLK Rise or Fall Time
tKHKL
CLK to WAIT Valid
tKHTL
tKHZ
tKLZ
tKOH
tKP
3
2
2
4
8
3
2
2
5
4
5
CLK to DQ High-Z Output
CLK to Low-Z Output
5
5
Output HOLD from CLK
CLK HIGH or LOW Time
Output Disable to DQ High-Z Output
Output Enable to Low-Z Output
Setup Time to Active CLK Edge
tOHZ
tOLZ
tSP
8
8
4
5
5
3
5
3
Notes: 1. All tests are performed with the outputs configured for full drive strength (BCR[5] = 0).
2. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-
vided every tCEM. A refresh opportunity is satisfied by either of the following two condi-
tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns.
3. Clock rates below 50 MHz (tCLK > 20ns) are allowed as long as tCSP specifications are met.
4. Low-Z to High-Z timings are tested with the circuit shown in Figure 25 on page 32. The
High-Z timings measure a 100mV transition from either VOH or VOL toward VCCQ/2.
5. High-Z to Low-Z timings are tested with the circuit shown in Figure 25 on page 32. The
Low-Z timings measure a 100mV transition away from the High-Z (VCCQ/2) level toward
either VOH or VOL.
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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