Connection Diagrams
Plastic Chip Carrier
Dual-In-Line Package
TL/H/5070–6
Top View
Order Number TP3064J or TP3067J
See NS Package J20A
Order Number TP3064WM or TP3067WM
See NS Package M20B
Order Number TP3064N or TP3067N
See NS Package N20A
TL/H/5070–2
Top View
Order Number TP3064V or TP3067V
See NS Package V20A
Pin Description
Symbol
MCLK
Function
Symbol
Function
Transmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be
X
VPOa
GNDA
VPOb
VPI
The non-inverted output of the receive power
amplifier.
asynchronous with MCLK . Best
R
performance is realized from synchronous
operation.
Analog ground. All signals are referenced to
this pin.
The inverted output of the receive power
amplifier.
BCLK
The bit clock which shifts out the PCM data
on D . May vary from 64 kHz to 2.048 MHz,
X
X
Inverting input to the receive power amplifier.
Analog output of the receive filter.
ea
but must be synchronous with MCLK .
X
VF O
R
V
D
X
The TRI-STATE PCM data output which is
É
enabled by FS .
X
g
5V 5%.
Positive power supply pin. V
CC
CC
FS
X
Transmit frame sync pulse input which
FS
Receive frame sync pulse which enables
BCLK to shift PCM data into D . FS is an
8 kHz pulse train. SeeFigures 2 and3 for
timing details.
R
enables BCLK to shift out the PCM data on
X
D . FS is an 8 kHz pulse train, seeFigures 2
R
R
R
X
X
and3 for timing details.
TS
X
Open drain output which pulses low during
the encoder time slot.
D
Receive data input. PCM data is shifted into
following the FS leading edge.
R
R
D
R
ANLB
Analog Loopback control input. Must be set
to logic ‘0’ for normal operation. When pulled
to logic ‘1’, the transmit filter input is
disconnected from the output of the transmit
preamplifier and connected to the VPOa
output of the receive power amplifier.
Analog output of the transmit input amplifier.
Used to externally set gain.
BCLK
/
The bit clock which shifts data into D after
R
the FS leading edge. May vary from 64 kHz
R
to 2.048 MHz. Alternatively, may be a logic
input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
R
CLKSEL
BCLK is used for both transmit and receive
X
directions (see Table I).
GS
X
VF Ib
X
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input
amplifier.
MCLK /
R
PDN
Receive master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be
VF Ia
X
asynchronous with MCLK , but should be
X
synchronous with MCLK for best
X
performance. When MCLK is connected
eb
g
5V 5%.
V
BB
Negative power supply pin. V
BB
R
continuously low, MCLK is selected for all
X
internal timing. When MCLK is connected
R
continuously high, the device is powered
down.
2
NSC [ National Semiconductor ]
