SPI modes
M25PE40
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
●
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in
is the clock polarity when the
bus master is in Standby mode and not transferring data:
●
●
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Bus master and memory devices on the SPI bus
V
SS
V
CC
R
SDO
SPI interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C Q D
SPI Bus Master
R
CS3
CS2 CS1
S
W Reset
or
TSL
S
W Reset
or
TSL
S
Reset
W
or
TSL
SPI memory
device
V
CC
V
SS
R
SPI memory
device
C Q D
V
CC
V
SS
R
SPI memory
device
C Q D
V
CC
V
SS
Figure 4.
AI13558b
1. The Write Protect or Top Sector Lock (W or TSL) signal should be driven, High or Low as appropriate.
shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in
ensure
that the M25PE40 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the t
SHCH
requirement is met). The
typical value of R is 100 kΩ, assuming that the time constant R*C
p
(C
p
= parasitic
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
10/62
NUMONYX [ NUMONYX B.V ]
