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M25PE40 参数 Datasheet PDF下载

M25PE40图片预览
型号: M25PE40
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位,页擦除串行闪存与字节变性, 75兆赫的SPI总线,标准引脚 [4 Mbit, page-erasable serial Flash memory with byte alterability, 75 MHz SPI bus, standard pinout]
分类和应用: 闪存
文件页数/大小: 62 页 / 1298 K
品牌: NUMONYX [ NUMONYX B.V ]
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M25PE40
Operating features
4.3
A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256
contiguous bytes at a time), provided that it only involves resetting bits to 0 that had
previously been set to ‘1’.
This might be:
when the designer is programming the device for the first time
when the designer knows that the page has already been erased by an earlier Page
Erase (PE) or Sector Erase (SE) instruction. This is useful, for example, when storing a
fast stream of data, having first performed the erase cycle when time was available
when the designer knows that the only changes involve resetting bits to ‘0’ that are still
set to ‘1’. When this method is possible, it has the additional advantage of minimizing
the number of unnecessary erase operations, and the extra stress incurred by each
page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see
and
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (t
PW
, t
PP
, t
PE
, or t
SE
). The Write In Progress (WIP) bit is provided in the
Status Register so that the application program can monitor its value, polling it to establish
when the previous cycle is complete.
4.5
Reset
An internal Power-on Reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset) Low during the power-on process, and only
driving it High when V
CC
has reached the correct voltage level, V
CC
(min).
4.6
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write). The device then goes
in to the Standby Power mode. The device consumption drops to I
CC1
.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to I
CC2
. The
device remains in this mode until the Release from Deep Power-down instruction is
executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
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