Operating features
M25PE40
4.7
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by using specific instructions. See
for a detailed description of the Status Register bits.
4.8
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
features the following data protection mechanisms:
4.8.1
Protocol-related protections
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●
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Power On Reset and an internal timer (t
PUW
) can provide protection against inadvertent
changes while the power supply is outside the operating specification.
Program, Erase and Write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
–
–
–
–
Power-up
Reset (Reset) driven Low
Write Disable (WRDI) instruction completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Write to Lock Register (WRLR) instruction completion
Page Erase (PE) instruction completion
Subsector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
●
The Reset (Reset) signal can be driven Low to freeze and reset the internal logic. For
the specific cases of Program and Write cycles, the designer should refer to
and to
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions while
the device is not in active use.
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