PE3342
Product Specification
Figure 2. Pin Configurations (Top View)
V
DD
GND
ENH
S_WR
Data
Clock
GND
FSel
E_WR
1
2
3
4
5
6
24
23
22
21
20
19
Figure 3. Package Types
24-lead TSSOP, 20-lead QFN
f
r
GND
EESel
17
PD_U
PD_D
V
DD
Dout
LD
EELoad
Cext
GND
F
in
S_WR
Data
Clock
FSel
E_WR
1
2
3
4
5
20
19
18
16
PD_U
EESel
ENH
V
DD
f
r
15
PD_D
V
DD
Dout
LD
EELoad
24-lead TSSOP
7
8
9
18
17
16
15
14
13
20-lead QFN
4x4mm
Exposed Solder Pad
(Bottom Side)
14
13
12
11
V
PP
10
V
DD
11
F
in
12
Table 2. Pin Descriptions
Pin No.
TSSOP
1
2
3
20
Pin No.
QFN
19
Pin Name
V
DD
GND
ENH
Type
(Note 1)
(Note 2)
Input
C
EXT
V
DD
V
PP
F
IN
F
INX
10
6
7
8
9
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Ground.
Enhancement mode control line. When asserted LOW, enhancement register bits are
functional. Internal 70 kΩ pull-up resistor.
Secondary Register WRITE input. Primary Register contents are copied to the
Secondary Register on S_WR rising edge. Also used to control Serial Port operation
and EEPROM programming.
Binary serial data input. Input data entered LSB (B
0
) first.
Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit
EE Register, or the 8-bit Enhancement Register on the rising edge of Clock. Also used
to clock EE Register data out Dout port.
Ground.
Frequency Register selection control line. Internal 70 kΩ pull-down resistor.
Enhancement Register write enable. Also functions as a Serial Port control line.
Internal 70 kΩ pull-down resistor.
EEPROM erase/write programming voltage supply pin. Requires a 100pF bypass
capacitor connected to GND.
Same as pin 1.
Prescaler input from the VCO.
Prescaler complementary input. A series 50
Ω
resistor and DC blocking
capacitor
should be placed as close as possible to this pin and connected to the ground plane.
Ground.
Logical “NAND” of PD_U and PD_D terminated through an on-chip, 2 kΩ
series
resistor.
Connecting C
EXT
to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Control line for Serial Data Port, Frequency Register selection, EE Register parallel
loading, and EEPROM programming. Internal 70 kΩ pull-down resistor.
Lock detect output, an open-drain logical inversion of C
EXT
. When the loop is in lock,
LD is high impedance; otherwise, LD is a logic LOW.
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
S_WR
Data
Clock
GND
Input
Input
Input
(Note 2)
Input
Input
Input
(Note 1)
Input
Input
(Note 2)
Output
Input
Output, OD
4
5
6
7
8
9
FSel
E_WR
V
PP
V
DD
F
in
F
in
GND
10
11
12
C
EXT
EELoad
LD
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 17
Document No. 70-0091-03
│
UltraCMOS™ RFIC Solutions
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
