PE9704
Advance Information
Figure 2. Pin Configuration
GND
GND
GND
ENH
V
DD
LD
R
3
R
2
R
1
R
0
F
R
6
R
4
R
5
M
0
M
1
V
DD
V
DD
M
2
M
3
S_WR, M
4
DATA, M
5
GND
5
4
3
2
1
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
C
EXT
V
DD
PD_U
PD_D
GND
N/C
V
DD
D
OUT
V
DD
N/C
GND
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
CLOCK, M
6
D
MODE
M
7
M
8
A
0
E_WR, A
1
A
2
A
3
V
DD
F
IN
GND
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
V
DD
R
0
R
1
R
2
R
3
GND
R
4
R
5
M
0
M
1
V
DD
V
DD
M
2
M
3
S_WR
M
4
Interface Mode
Both
Direct
Direct
Direct
Direct
Both
Direct
Direct
Direct
Direct
Both
Both
Direct
Direct
Serial
Direct
Serial
Type
(Note 1)
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
(Note 1)
(Note 1)
Input
Input
Input
Input
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing
recommended.
R Counter bit0
R Counter bit1
R Counter bit2
R Counter bit3
Ground
R Counter bit4
R Counter bit5 (MSB)
M Counter bit0
M Counter bit1
Same as pin 1
Same as pin 1
M Counter bit2
M Counter bit3
Frequency register load enable input. Buffered data is transferred to the frequency
register on S_WR rising edge.
M Counter bit4
Binary serial data input. Data is entered LSB first, and is clocked serially into the 20-
bit frequency control register (E_WR “low”) or the 8-bit enhancement register (E_WR
“high”) on the rising edge of CLOCK.
15
16
DATA
Copyright
Peregrine Semiconductor Corp. 2003
File No. 70/0083~00B
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UTSi
CMOS RFIC SOLUTIONS
Page 2 of 12
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