MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
tion. hange.
cifica
c
al spe ubject to
a fin
s
is not limits are
is ric
e: Th
t
Notice parame
m
So
PR
Y
INAR
ELIM
PS12017-A
FLAT-BASE TYPE
INSULATED TYPE
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART.
N-side IGBT Current
off
N-side FWDi Current
V
CIN
V(hold)
I
C
on
on
off
0
+I
CL
(V
S
)
0
–I
CL
t(hold)
Ref
V
C
0
off
V
CL
on
Delay time
td(read)
Fig. 9 START-UP SEQUENCE
Normally at start-up, Fo and CL output signals will be pulled-up
High to V
DL
voltage (OFF level); however, F
O1
output may fall to
Low (ON) level at the instant of the first ON input pulse to an N-Side
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. F
O1
resetting sequence (together with the boot-strap
charging sequence) is explained in the following graph
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
V
DL
(5V)
5.1kΩ
R
ASIPM
U
P
,V
P
,W
P
,U
N
,V
N
,W
N
,Br
DC-Bus voltage
Control voltage supply
Boot-strap voltage
N-Side input signal
P-Side input signal
Brake input signal
F
O
1 output signal
V
PN
0
V
DH, DL
0
V
DB
V
CIN(N)
0
on
PWM starts
a)
R
CPU
10kΩ
CU,CV,CW
F
O1
,F
O2
,F
O3
,CL
b)
0.1nF
0.1nF
GND(Logic)
V
CIN(P)
on
V
CIN(Br)
on
F
OI
on
a) Boot-strap charging scheme :
Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20µs number of pulses =10 ~ 500 de-
pending on the boot-strap capacitor size)
b) F
O1
resetting sequence:
Apply ON signals to the following input pins : Br
→
Un/Vn/Wn
→
Up/Vp/Wp in that order.
Jan. 2000
POWEREX [ POWEREX POWER SEMICONDUCTORS ]
