P3C1024L
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)
(6)
CE
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Fig. 1 and 2
TRUTH TABLE
Mode
Standby
Standby
Output
Disabled
Read
Write
CE
1
CE
2
OE WE
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
X
X
H
H
L
I/O
High Z
High Z
High Z
D
OUT
D
IN
Power
Standby
Standby
Active
Active
Active
Figure 1. Output Load
* including scope and test fixture.
Figure 2. Thevenin Equivalent
Note:
Because of the high speed of the P3C1024L, care must be taken
when testing this device; an inadequate setup can cause a normal
functioning part to be rejected as faulty. Long high-inductance
leads that cause supply bounce must be avoided by bringing the V
CC
and ground planes directly up to the contactor fingers. A 0.01 µF
high frequency capacitor is also required between V
CC
and ground.
To avoid signal reflections, proper termination must be used; for
example, a 50Ω test environment should be terminated into a 50Ω
load with 1.75V (Thevenin Voltage) at the comparator input, and a
595Ω resistor must be used in series with D
OUT
to match 645Ω
(Thevenin Resistance).
Document #
SRAM132
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