Internet Data Sheet
HY[B/I]39S256[40/80/16][0/7]F[E/T/F](L)
256-MBit Synchronous DRAM
2
Configuration
This chapter contains the pin configuration table, the TSOP and FBGA package drawing, and the block diagrams for the ×4,
×8, ×16 organization of the SDRAM.
2.1
Pin Description
Listed below are the pin configurations sections for the various signals of the SDRAM.
TABLE 4
Pin Configuration of the SDRAM
Ball No. Name Pin
Buffer
Function
Type Type
Clock Signals ×4/×8/×16 Organization
38,2F
CLK
CKE
I
I
LVTTL
LVTTL
Clock Signal CK
Clock Enable
37, 3F
Control Signals ×4/×8/×16 Organization
18, 8F
17, 7F
16, 9F
19, 9G
RAS
CAS
WE
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write Enable (WE)
CS
Chip Select
Address Signals ×4/×8/×16 Organization
20, 7G
21, 8G
23, 7H
24, 8H
25, 8J
26, 7J
29, 3J
30, 2J
31, 3H
32, 2H
33, 1H
34, 3G
22, 9H
35, 2G
36, 1G
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Bank Address Signals 1:0
Address Signal 12:0, Address Signal 10/Auto precharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
Rev. 1.42, 2007-09
6
03292006-TMTK-JFEU
QIMONDA [ QIMONDA AG ]
