TFP401, TFP401A
TI
PanelBus
DIGITAL RECEIVER
SLDS120B - MARCH 2000 – REVISED JUNE 2003
functional block diagram
3.3 V
3.3 V
1.8 V
Regulator
Internal 50-Ω
Termination
RED(0-7)
Rx2+
Rx2-
Rx1+
Rx1-
Rx0+
Rx0-
+
_
Channel 2
Latch
Channel 1
Latch
Channel 0
Latch
CH2(0-9)
CTL3
CTL2
Data Recovery CH1(0-9)
TMDS
and
Decoder
Synchronization
CH0(0-9)
3.3 V
71
44
51
8
Panel
Interface
+
_
GRN(0-7)
CTL1
RxC+
RxC-
+
_
PLL
Terminal Functions
TERMINAL
NAME
AGND
AVDD
CTL[3:1]
DE
NO.
79,83,87,
89,92
82,84,88,
95
42,41,40
46
I/O
GND
VDD
DO
DO
Analog Ground – Ground reference and current return for analog circuitry.
Analog VDD – Power supply for analog circuitry. Nominally 3.3 V
General-purpose control signals – Used for user defined control. CTL1 is not powered-down via PDO.
Output data enable – Used to indicate time of active video display versus non-active display or blank time.
During blank, only HSYNC, VSYNC, and CTL1-3 are transmitted. During times of active display, or non-blank,
only pixel data, QE[23:0] and QO[23:0], is transmitted.
DFO
1
DI
讯
DVDD
EXT_RES
HSYNC
RSVD
OVDD
ODCK
金
DGND
5,39,68
合
GND
VDD
AI
DO
DI
VDD
DO
6,38,67
96
48
99
18,29,43,
57,78
44
市
圳
深
科
技
Output clock data format – Controls the output clock (ODCK) format for either TFT or DSTN panel support. For
TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high, otherwise
ODCK is held low when DE is low.
High : DSTN support/ODCK held low when DE = low
Low: TFT support/ODCK runs continuously.
Digital ground – Ground reference and current return for digital core
Digital VDD – Power supply for digital core. Nominally 3.3 V
Internal impedance matching – The TFP401/40A is internally optimized for impedance matching at 50
Ω.
An
external resistor tied to this pin will have no effect on device performance.
Horizontal sync output
Reserved. Must be tied high for normal operation.
Output driver VDD – Power supply for output drivers. Nominally 3.3 V
Output data clock - Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with
DE, HSYNC, VSYNC and CTL[3:1] are synchronized to this clock.
有
High : Active display time
Low: Blank time
限
公
司
，
18
66
43
41
5
DESCRIPTION
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
85
，
QQ
：
+
_
BLU(0-7)
VSYNC
HSYNC
19
QE(0-23)
QO(0-23)
ODCK
DE
SCDT
CTL3
CTL2
CTL1
VSYNC
HSYNC
3
QUANTUM [ QUANTUM RESEARCH GROUP ]
