TFP401, TFP401A
TI
PanelBus
DIGITAL RECEIVER
SLDS120B - MARCH 2000 – REVISED JUNE 2003
Terminal Functions (continued)
TERMINAL
NAME
OGND
OCK_INV
NO.
19,28,45,
58,76
100
I/O
GND
DI
DESCRIPTION
Output driver ground – Ground reference and current return for digital output drivers
ODCK Polarity – Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals
(HSYNC, VSYNC, DE, CTL1-3 ) are latched
Normal Mode:
High : Latches output data on rising ODCK edge
Low : Latches output data on falling ODCK edge
PD
2
DI
Power down – An active low signal that controls the TFP401/401A power-down state. During power down all
output buffers are switched to a high impedance state. All analog circuits are powered down and all inputs are
disabled, except for PD.
If PD is left unconnected an internal pullup will default the TFP401/401A to normal operation.
High : Normal operation
Low: Power down
High : Normal operation/output drivers on
Low: Output drive power down.
PGND
PIXS
4
98
GND
DI
High : 2-pixel/clock
Low: 1-pixel/clock
20-27
QO[0:7]
49-56
DO
QO[8:15]
59-66
金
合
DO
市
深
QO[16:23]
圳
69-75,77
DO
QE[0:7]
10-17
DO
讯
科
LSB: QE16/pin 30
MSB: QE23/pin 37
Odd blue pixel output – Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO0/pin 49
MSB: QO7/pin 56
Odd green pixel output – Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low,
when in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO8/pin 59
MSB: QO15/pin 66
Odd red pixel output – Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when
in 1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QO16/pin 69
MSB: QO23/pin 77
Even blue pixel output – Output for even and odd blue pixels when in 1-pixel/clock mode. Output for even only
blue pixel when in 2-pixel per clock mode. Output data is synchronized to the output data clock, ODCK.
LSB: QE0/pin 10
MSB: QE7/pin 17
技
有
QE[16:23]
30-37
DO
Even red pixel output – Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only
red pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
限
LSB: QE8/pin 20
MSB: QE15/pin 27
公
Even green pixel output – Output for even and odd green pixels when in 1-pixel/clock mode. Output for even
only green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.
司
PVDD
QE[8:15]
97
VDD
DO
PLL VDD – Power supply for internal PLL
，
4
POST OFFICE BOX 655303
18
•
DALLAS, TEXAS 75265
66
Pixel select – Selects between one or two pixels per clock output modes. During the 2-pixel/clock mode, both
even pixels, QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During
1-pixel/clock, even and odd pixels are output sequentially, one at a time, with the even pixel first, on the even
pixel bus, QE[23:0]. (The first pixel per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the
odd pixel.)
43
41
5
PLL GND – Ground reference and current return for internal PLL
85
，
QQ
PDO
9
DI
Output drive power down – An active low signal that controls the power-down state of the output drivers.
During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high impedance
state. When PDO is left unconnected, an internal pullup defaults the TFP401/401A to normal operation.
：
71
44
51
8
19
QUANTUM [ QUANTUM RESEARCH GROUP ]
