TFP401, TFP401A
TI
PanelBus
DIGITAL RECEIVER
SLDS120B - MARCH 2000 – REVISED JUNE 2003
Terminal Functions (continued)
TERMINAL
NAME
RxC+
RxC–
Rx0+
Rx0–
Rx1+
Rx1–
Rx2+
Rx2–
SCDT
NO.
93
94
90
91
85
86
80
81
8
I/O
AI
AI
AI
AI
AI
AI
AI
AI
DO
DESCRIPTION
Clock positive receiver input – Positive side of reference clock. TMDS low voltage signal differential input pair
Clock negative receiver input – Negative side of reference clock. TMDS low voltage signal differential input
pair.
Channel-1 positive receiver input – Positive side of channel-1 TMDS low voltage signal differential input pair.
Channel-1 receives green pixel data in active display and CTL1 control signals in blank.
Channel-1 negative receiver input – Negative side of channel-1 TMDS low voltage signal differential input pair
Channel-2 negative receiver input – Negative side of channel-2 TMDS low voltage signal differential input pair.
ST
3
DI
VSYNC
47
DO
Vertical sync output
深
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Specified with PowerPAD bond pad on the backside of the package soldered to a 2 oz. Cu plate PCB thermal plane. Specified
at maximum allowed operating temperature, 70°C.
2. PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating
temperature, 70°C.
圳
Supply voltage range, DV
DD
, AV
DD
, OV
DD
, PV
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V
Input voltage range, logic/analog signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 4 V
Operating ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65°C to 150°C
Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Package power dissipation/PowerPAD: Soldered (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 W
Not soldered (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 W
ESD Protection, all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 KV Human Body Model
JEDEC latchup (EIA/JESD78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
市
金
合
讯
科
技
有
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
限
公
司
High : Normal simultaneous even/odd pixel output
Low: Time staggered even/odd pixel output
，
18
STAG
7
DI
Staggered pixel select – An active low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time staggers
the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels
simultaneously.
66
Output drive strength select – Selects output drive strength for high or low current drive. (See dc specifications
for IOH and IOL vs ST state.)
High : High drive strength
Low : Low drive strength
43
41
5
High: Active link
Low: Inactive link
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
85
，
Sync detect – Output to signal when the link is active or inactive. The link is considered to be active when DE is
actively switching. The TFP401/401A monitors the state DE to determine link activity. SCDT can be tied
externally to PDO to power down the output drivers when the link is inactive.
QQ
：
Channel-2 positive receiver input – Positive side of channel-2 TMDS low voltage signal differential input pair.
Channel-2 receives red pixel data in active display and CTL2, CTL3 control signals in blank.
71
44
51
8
Channel-0 negative receiver input – Negative side of channel-0. TMDS low voltage signal differential input
pair.
19
Channel-0 positive receiver input – Positive side of channel-0. TMDS low voltage signal differential input pair.
Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.
5
QUANTUM [ QUANTUM RESEARCH GROUP ]
