RF3266
Preliminary Application Schematic
V
CC
V
CCBIAS
TBD nH
NOTES:
* Optional Component
** Place these capacitors as close to
PA as possible.
TBD
nH
An inductor may be required to
isolate VCC1 from VCC2
depending on the layout.
4.7
μF
4.7
μF*
1 nF
1 nF
1 nF**
16
15
14
Interstage MN
Q1
IMN
Q2
Depending on the degree of HPM isolation
from LPM this inductor may become
optional and potentially be replaced with a
copper trace on the PCB.
13
12
4.7
μF
RF IN
1
2
11
1 nF**
VMODE
1 nF*
3
Bias
OMN
Integrated
Power Detector
10
4
VREG
1 nF
R1
3.6 kΩ
R3
SUT
Ω
5
9
8
RF OUT
6
7
R2
SUT
Ω
R1 = 3.6 kΩ typ. This load resistor determines the
detector sensitivity. An internal 15 pF capacitor is in
parallel with this load resistor.
R3 is optional and may be used in conjunction with
R2 to scale PDET (max) if desired.
This capacitor is used in conjunction with R1, R2 and
R3 to set the rise and fall time of the detected output
voltage, and tradeoff acceptable voltage ripple versus
rise/fall time.
SUT nF
SUT = Select Under Test
VDET
Rev A0 DS070529
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
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