K4J55323QG
WRITE LATENCY
256M GDDR3 SDRAM
The Write latency (WL) is the delay, in clock cycles, between the registration of a WRITE command and the availability of the first bit of
input data. The latency can be set from 1 to 7 clocks depending in the operating frequency and desired current draw. When the write
latencies are set to 1 or 2 or 3 clocks, the input receivers never turn off when the WRITE command is registered. If a WRITE command
is registered at clock edge
n,
and the latency is
m
clocks, the data will be available nominally coincident with clock edge
n+m.
Reserved
states should not be used as unknown operation or incompatibility with future versions may result.
T0
/CK
CK
COMMAND
T1
T2
T3
T3n
WRITE
NOP
WL = 3
NOP
NOP
WDQS
DQ
T0
T2
T3
T4
T4n
∼ ∼ ∼ ∼
∼ ∼ ∼ ∼
/CK
CK
COMMAND
WRITE
NOP
WL = 4
NOP
NOP
WDQS
DQ
Burst Length = 4 in the cases shown
DON’T CARE
TRANSITIONING DATA
12 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
