K4J55323QG
CAS LATENCY (READ LATENCY)
256M GDDR3 SDRAM
The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output
data. The latency can be set to 4~15 clocks. If a READ command is registered at clock edge
n,
and the latency is
m
clocks, the data will
be available nominally coincident with clock edge
n+m.
Below table indicates the operating frequencies at which each CAS latency set-
ting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
CAS Latency
SPEED
-10
-11
-12
-14
Allowable operating frequency (MHz)
CL=15
CL=14
TBD
TBD
≤
800
-
≤
700
-
-
≤
600
-
-
-
-
CL=13
CL=12
CL=11
CL=10
CL=9
CL=8
CL=7
-16
-20
-
-
-
-
-
-
-
≤
500
T0
T5
T6
T7
T7n
∼ ∼∼ ∼
∼ ∼∼ ∼
/CK
CK
COMMAND
READ
NOP
CL = 7
NOP
NOP
RDQS
DQ
T0
T6
T7
T8
T8n
∼ ∼∼ ∼
∼ ∼∼ ∼
/CK
CK
COMMAND
READ
NOP
CL = 8
NOP
NOP
RDQS
DQ
Burst Length = 4 in the cases shown
Shown with nominal t
AC
and nominal t
DSDQ
DON’T CARE
TRANSITIONING DATA
11 of 53
Rev. 1.1 November 2005
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
