K4S641632F
1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
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JEDEC standard 3.3V power supply
LVTTL compatible with multiplexed address
Four banks operation
MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst read single-bit write operation
DQM for masking
Auto & self refresh
64ms refresh period (4K cycle)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S641632F is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 16
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
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ORDERING INFORMATION
Part No.
K4S641632F-TC50/TL50
K4S641632F-TC55/TL55
K4S641632F-TC60/TL60
K4S641632F-TC70/TL70
K4S641632F-TC75/TL75
K4S641632F-TC1H/TL1H
K4S641632F-TC1L/TL1L
Max Freq.
200MHz(CL=3)
183MHz(CL=3)
166MHz(CL=3)
143MHz(CL=3)
133MHz(CL=3)
100MHz(CL=2)
100MHz(CL=3)
LVTTL
54
TSOP(II)
Interface Package
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
LDQM
Data Input Register
Bank Select
1M x 16
Sense AMP
1M x 16
1M x 16
1M x 16
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Timing Register
Programming Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
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Samsung Electronics reserves the right to change products or specification without notice.
Rev.0.1 Sept. 2001
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
