K4S641632F
AC OPERATING TEST CONDITIONS
(V
DD
= 3.3V
±
0.3V, T
A
= 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
3.3V
CMOS SDRAM
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Vtt = 1.4V
Unit
V
V
ns
V
1200Ω
V
OH
(DC) = 2.4V, I
OH
= -2mA
50Ω
V
OL
(DC) = 0.4V, I
OL
= 2mA
Output
870Ω
50pF
Output
Z0 = 50Ω
50pF
(Fig. 1) DC output load circuit
Notes :
1. The DC/AC Test Output Load of K4S641632F-50/55/60 is 30pF.
2. The VDD condition of K4S641632F-50/55/60 is 3.135V~3.6V.
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to active delay
Last data in to new col. address Delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output
data
Symbol
-50
t
RRD
(min)
t
RCD
(min)
t
RP
(min)
t
RAS
(min)
t
RAS
(max)
t
RC
(min)
t
RDL
(min)
t
DAL
(min)
t
CDL
(min)
t
BDL
(min)
t
CCD
(min)
2CLK
+15ns
2CLK
+16.5ns
2CLK
+18ns
55
55
60
10
15
15
40
-55
11
16.5
16.5
38.5
-60
12
18
18
42
Version
-70
14
20
20
49
100
68
2
2CLK
+20ns
1
1
1
2
-
1
2CLK
+20ns
2CLK
+20ns
2CLK
+20ns
65
70
70
-75
15
20
20
45
-1H
20
20
20
50
-1L
20
20
20
50
ns
ns
ns
ns
us
ns
CLK
-
CLK
CLK
CLK
ea
1
2,5
5
2
2
3
4
1
1
1
1
Unit
Note
CAS latency=3
CAS latency=2
Notes :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev.0.1 Sept. 2001
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
