K4S641632F
CMOS SDRAM
1M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
The K4S641632F is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 16
bits, fabricated with SAMSUNG¢s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
• Auto & self refresh
• 64ms refresh period (4K cycle)
K4S641632F-TC50/TL50 200MHz(CL=3)
K4S641632F-TC55/TL55 183MHz(CL=3)
K4S641632F-TC60/TL60 166MHz(CL=3)
K4S641632F-TC70/TL70 143MHz(CL=3)
K4S641632F-TC75/TL75 133MHz(CL=3)
K4S641632F-TC1H/TL1H 100MHz(CL=2)
K4S641632F-TC1L/TL1L 100MHz(CL=3)
54
LVTTL
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
1M x 16
1M x 16
1M x 16
1M x 16
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
Samsung Electronics reserves the right to change products or specification without notice.
*
Rev.0.1 Sept. 2001
SAMSUNG [ SAMSUNG ]
