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K4S641632F-TL75 参数 Datasheet PDF下载

K4S641632F-TL75图片预览
型号: K4S641632F-TL75
PDF下载: 下载PDF文件 查看货源
内容描述: 64Mbit的SDRAM 1M X 16Bit的×4银行同步DRAM LVTTL [64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL]
分类和应用: 动态存储器
文件页数/大小: 11 页 / 135 K
品牌: SAMSUNG [ SAMSUNG ]
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K4S641632F  
CMOS SDRAM  
PIN CONFIGURATION (Top view)  
VDD  
DQ0  
VDDQ  
DQ1  
DQ2  
VSSQ  
DQ3  
DQ4  
VDDQ  
1
2
3
4
5
6
7
8
9
VSS  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
DQ15  
VSSQ  
DQ14  
DQ13  
VDDQ  
DQ12  
DQ11  
VSSQ  
DQ10  
DQ9  
VDDQ  
DQ8  
VSS  
N.C/RFU  
UDQM  
CLK  
CKE  
N.C  
A11  
A9  
DQ5 10  
DQ6 11  
VSSQ  
12  
DQ7 13  
14  
VDD  
LDQM 15  
WE 16  
CAS 17  
RAS 18  
CS 19  
BA0 20  
BA1 21  
A10/AP 22  
A8  
A7  
A6  
A5  
A4  
VSS  
A0  
A1  
A2  
A3  
VDD  
23  
24  
25  
26  
27  
54Pin TSOP (II)  
(400mil x 875mil)  
(0.8 mm Pin pitch)  
PIN FUNCTION DESCRIPTION  
Pin  
Name  
System clock  
Input Function  
CLK  
CS  
Active on the positive going edge to sample all inputs.  
Disables or enables device operation by masking or enabling all inputs except  
CLK, CKE and L(U)DQM  
Chip select  
Masks system clock to freeze operation from the next clock cycle.  
CKE should be enabled at least one cycle prior to new command.  
Disable input buffers for power down in standby.  
CKE  
Clock enable  
Row/column addresses are multiplexed on the same pins.  
Row address : RA0 ~ RA11, Column address : CA0 ~ CA7  
A0 ~ A11  
BA0 ~ BA1  
RAS  
Address  
Selects bank to be activated during row address latch time.  
Selects bank for read/write during column address latch time.  
Bank select address  
Row address strobe  
Column address strobe  
Write enable  
Latches row addresses on the positive going edge of the CLK with RAS low.  
Enables row access & precharge.  
Latches column addresses on the positive going edge of the CLK with CAS low.  
Enables column access.  
CAS  
Enables write operation and row precharge.  
Latches data in starting from CAS, WE active.  
WE  
Makes data output Hi-Z, tSHZ after the clock and masks the output.  
Blocks data input when L(U)DQM active.  
L(U)DQM  
Data input/output mask  
DQ0 ~ 15  
VDD/VSS  
Data input/output  
Data inputs/outputs are multiplexed on the same pins.  
Power and ground for the input buffers and the core logic.  
Power supply/ground  
Isolated power supply and ground for the output buffers to provide improved noise  
immunity.  
VDDQ/VSSQ  
N.C/RFU  
Data output power/ground  
No connection  
/reserved for future use  
This pin is recommended to be left No Connection on the device.  
Rev.0.1 Sept. 2001