S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
PIN DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Symbol
MCP
DCB
FRSH
DCC2
DCC1
FSET
VDDA
VCCP
GC2I
GC2O
CH2I
CH2O
CH1O
CH1I
GC1O
GC1I
RRC
VSSP
MUTEI
ISET
VREG
WDCK
SMDP
SMON
SMEF
FLB
FS3
FGD
LOCK
TRCNT
ISTAT
Description
Capacitor connection pin for mirror hold
Capacitor connection pin for defect Bottom hold
Capacitor connection pin for time constant to generate focus search waveform
The input pin through capacitor of defect bottom hold output
The output pin of defect bottom hold
The peak frequency setting pin for focus, tracking servo and cut off frequency of CLV
LPF
Analog VCC for servo part
VCC for post filter
Amplifier negative input pin for gain and low pass filtering of DAC output CH2
Amplifier output pin for gain and low pass filtering of DAC output CH2
The input pin for post filter channel2
The output pin for post filter channel2
The output pin for post filter channel1
The input pin for post filter channel1
Amplifier output pin for gain and low pass filtering of DAC output CH1
Amplifier negative input pin for gain and low pass filtering of DAC output CH1
The pin for noise reduction of post filter bias
VSS for post filter
The input pin for post filter muting control
The input pin for current setting of focus search, track jump and sled kick voltage
The output pin of regulator
The clock input pin for auto sequence
The input pin of CLV control output pin SMDP of DSP
The input pin for spindle servo ON through SMON of DSP
The input pin of provide for an external LPF time constant
Capacitor connection pin to perform rising low bandwidth of focus loop
The pin for high frequency gain change of focus loop with internal FS3 switch
Reducing high frequency gain with capacitor between FS3 pin
Sled runaway prevention pin
Track count output pin
Internal status output pin
4
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
