Si1010/1/2/3/4/5
1.3. Port Input/Output
Digital and analog resources are available through 12 I/O pins. Port pins are organized as three byte-wide
ports. Port pins P0.0–P1.6 can be defined as digital or analog I/O. Digital I/O pins can be assigned to one
of the internal digital resources or used as general purpose I/O (GPIO). Analog I/O pins are used by the
internal analog resources. P1.0, P1.1, P1.2, and P1.3 are dedicated for communication with the EZRadio-
PRO peripheral. P2.7 can be used as GPIO and is shared with the C2 Interface Data signal (C2D). See
The designer has complete control over which digital and analog functions are assigned to individual Port
pins, limited only by the number of physical I/O pins. This resource assignment flexibility is achieved
through the use of a Priority Crossbar Decoder. See Section “21.3. Priority Crossbar Decoder” on
All Px.x Port I/Os are 5 V tolerant when used as digital inputs or open-drain outputs. For Port I/Os config-
ured as push-pull outputs, current is sourced from the VDD/DC+ supply. Port I/Os used for analog func-
tions can operate up to the VDD/DC+ supply voltage. See Section “21.1. Port I/O Modes of Operation” on
detailed electrical specifications.
XBR0, XBR1,
XBR2, PnSKIP
Registers
Port Match
P0MASK, P0MAT
P1MASK, P1MAT
Priority
Decoder
Highest
Priority
UART
SPI0
SPI1
(Internal Digital Signals)
SMBus
CP0
CP1
Outputs
SYSCLK
PCA
Lowest
Priority
T0, T1
7
2
8
P0
(Port Latches)
(P0.0-P0.7)
7
P1
(P1.0-P1.6)
1
P2
(P2.7)
To Analog Peripherals
(ADC0, CP0, and CP1 inputs,
VREF, IREF0, AGND)
1
P2
I/O
Cell
2
4
2
External Interrupts
EX0 and EX1
PnMDOUT,
PnMDIN Registers
P0.0
Digital
Crossbar
4
8
P0
I/O
Cells
P0.7
P1.4
P1
I/O
Cells
P1.5
P1.6
7
P2.7
No analog functionality
available on P2.7
Note: P1.0, P1.1, P1.2, and P1.3 are internally
connected to the EZRadioPRO peripheral.
Figure 1.9. Port I/O Functional Block Diagram
26
Rev. 1.0
SILABS [ SILICON LABORATORIES ]
