LAN9303 参数 Datasheet PDF下载

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Datasheet

7.3.1.3

Virtual PHY Pause Flow Control

The Virtual PHY supports pause flow control per the IEEE 802.3 specification. The Virtual PHYs

advertised pause flow control abilities are set via the

and

bits of

the

This allows the Virtual

PHY to advertise its flow control abilities and auto-negotiate the flow control settings with the emulated

link partner. The default values of these bits are as shown in

The symmetric/asymmetric pause ability of the emulated link partner is based upon the advertised

pause flow control abilities of the Virtual PHY as indicated in the

and

bits of the

Thus, the

emulated link partner always accommodates the asymmetric/symmetric pause ability settings

requested by the Virtual PHY, as shown in

The pause flow control settings may also be manually set via the

This register allows the Switch Fabric Port 0 flow control settings to be manually

set when auto-negotiation is disabled or the

bit is set. The currently enabled duplex and flow control settings can also be

monitored via this register. The flow control values in the

are not affected by the values of the manual flow control register. Refer to

for additional information.

7.3.2

Virtual PHY in MAC Mode

In the MAC mode of operation, an external PHY is connected to the MII interface of the device.

Because there is an external PHY present, the Virtual PHY is not needed for external configuration.

However, the Port 0 Switch Fabric MAC still requires the proper duplex setting. Therefore, in MAC

mode, if the

bit of the

is set, the duplex is based on the P0_DUPLEX pin and

configuration strap. If these signals are equal, the Port 0 Switch Fabric MAC is configured for full-

duplex, otherwise it is set for half-duplex. The P0_DUPLEX pin is typically connected to the duplex

indication of the external PHY. The duplex is not latched since the auto-negotiation process is not used.

The duplex can be manually selected by clearing the

bit and controlling

t h e

b i t i n t h e

Note:

In MAC mode, the Virtual PHY registers are accessible through their memory mapped registers

via the SMI or I

2

C serial management interfaces only. The Virtual PHY registers are not

accessible through MII management.

7.3.2.1

Full-Duplex Flow Control

In the MAC mode of operation, the Virtual PHY is not applicable. Therefore, full-duplex flow control

should be controlled manually by the host via the

based on the external PHYs auto-negotiation results.

7.3.3

Virtual PHY Resets

In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY

supports two block specific resets. These are is discussed in the following sections. For detailed

information on all resets, refer to

7.3.3.1

Virtual PHY Software Reset via RESET_CTL

The Virtual PHY can be reset via the

by setting the

bit. This bit is self clearing after approximately 102uS.

Revision 1.3 (08-27-09)

DATASHEET

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SMSC LAN9303/LAN9303i