Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
8.3.1
I
2
C EEPROM Device Addressing
The I
2
C EEPROM is addressed for a read or write operation by first sending a control byte followed
by the address byte or bytes. The control byte is preceded by a start condition. The control byte and
address byte(s) are each acknowledged by the EEPROM slave. If the EEPROM slave fails to send an
acknowledge, then the sequence is aborted and the
bit
of the
is set.
The control byte consists of a 4-bit control code, 3-bits of chip/block select and one direction bit. The
control code is 1010b. For single byte addressing EEPROMs, the chip/block select bits are used for
address bits 10, 9, and 8. For double byte addressing EEPROMs, the chip/block select bits are set
low. The direction bit is set low to indicate the address is being written.
illustrates typical I
2
C EEPROM addressing bit order for single and double byte addressing.
Control Byte
A
A
Address Byte
A
Control Byte
Address High
Byte
A A A A A A A
A
Address Low
Byte
A
S 1 0 1 0
1
A A
A A A A A A A A
C
0
C
9 8
7 6 5 4 3 2 1 0
K
0
K
S 1 0 1 0 0 0 0 0
C 1 1 1 1 1 1
A A
A A A A A A A A
C
C
9 8
K
7 6 5 4 3 2 1 0
K
K 5 4 3 2 1 0
Chip / Block R/~W
Select Bits
Single Byte Addressing
Chip / Block
Select Bits
R/~W
Double Byte Addressing
Figure 8.2 I
2
C EEPROM Addressing
8.3.2
I
2
C EEPROM Byte Read
Following the device addressing, a data byte may be read from the EEPROM by outputting a start
condition and control byte with a control code of 1010b, chip/block select bits as described in
and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by 8-
bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and
the
bit in the
is set. The I
2
C master then sends a no-acknowledge, followed by a stop condition.
illustrates typical I
2
C EEPROM byte read for single and double byte addressing.
Control Byte
Data Byte
Control Byte
Data Byte
A
A
A
A A
D D D D D D D D
A
C
S 1 0 1 0
1
1
C
C
P
0
9 8
K
K
7 6 5 4 3 2 1 0
K
A
A
D D D D D D D D
A
C
S 1 0 1 0 0 0 0 1
C
C
P
K
K
7 6 5 4 3 2 1 0
K
Chip / Block R/~W
Select Bits
Single Byte Addressing Read
Chip / Block R/~W
Select Bits
Double Byte Addressing Read
Figure 8.3 I
2
C EEPROM Byte Read
For a register level description of a read operation, refer to
Revision 1.3 (08-27-09)
DATASHEET
108
SMSC LAN9303/LAN9303i
SMSC [ SMSC CORPORATION ]
