LAN9303 参数 Datasheet PDF下载

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII

Datasheet

displays the various bus states of a typical I

2

C cycle.

data

can

change

data

stable

data

can

change

data

can

change

data

stable

data

can

change

EE_SDA

S

Sr

P

EE_SCL

Start Condition

Data Valid

or Ack

Re-Start

Condition

Data Valid

or Ack

Stop Condition

Figure 8.1 I

2

C Cycle

8.3

I

2

C Master EEPROM Controller

The I

2

C EEPROM controller supports I

2

C compatible EEPROMs.

Note:

When the EEPROM Loader is running, it has exclusive use of the I

2

C EEPROM controller.

Refer to

for more information.

The I

2

C master implements a low level serial interface (start and stop condition generation, data bit

transmission and reception, acknowledge generation and reception) for connection to I2C EEPROMs,

and consists of a data wire (EE_SDA) and a serial clock (EE_SCL). The serial clock is driven by the

master, while the data wire is bi-directional. Both signals are open-drain and require external pull-

upresistors.

The I

2

C master interface runs at the standard-mode rate of 100KHz and is fully compliant with the NXP

I

2

C-Bus Specification

. Refer to the he NXP I

2

C-Bus Specification

for detailed timing information.

Based on the

configuration strap, various sized I

2

C EEPROMs are supported. The

varying size ranges are supported by additional bits in the

field of the

Within each size range, the

largest EEPROM uses all the address bits, while the smaller EEPROMs treat the upper address bits

as don’t cares. The EEPROM controller drives all the address bits as requested regardless of the

actual size of the EEPROM. The supported size ranges for I

2

C operation are shown in

Table 8.1 I

2

C EEPROM Size Ranges

eeprom_size_strap

# OF ADDRESS BYTES

EEPROM SIZE

EEPROM TYPES

0

1

1 (Note

2

16 x 8 through 2048 x 8

4096 x 8 through 65536 x 8

24xx00, 24xx01, 24xx02,

24xx04, 24xx08, 24xx16

24xx32, 24xx64, 24xx128,

24xx256, 24xx512

Note 8.1

Bits in the control byte are used as the upper address bits.

SMSC LAN9303/LAN9303i

DATASHEET

107

Revision 1.3 (08-27-09)