Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
8.4
EEPROM Loader
The EEPROM Loader interfaces to the I
2
C EEPROM controller, the PHYs, and to the system CSRs
(via the Register Access MUX). All system CSRs are accessible to the EEPROM Loader.
The EEPROM Loader runs upon a pin reset (nRST), power-on reset (POR), digital reset (Digital
bit in the
or upon the issuance of a RELOAD
command via the
Refer to
for additional information on resets.
The EEPROM contents must be loaded in a specific format for use with the EEPROM Loader. An
overview of the EEPROM content format is shown in
Each section of EEPROM contents is
discussed in detail in the following sections.
Table 8.2 EEPROM Contents Format Overview
EEPROM ADDRESS
DESCRIPTION
VALUE
0
1
2
3
4
5
6
7
8 - 11
12
13
14 and above
EEPROM Valid Flag
MAC Address Low Word [7:0]
MAC Address Low Word [15:8]
MAC Address Low Word [23:16]
MAC Address Low Word [31:24]
MAC Address High Word [7:0]
MAC Address High Word [15:8]
Configuration Strap Values Valid Flag
Configuration Strap Values
Burst Sequence Valid Flag
Number of Bursts
Burst Data
A5h
1
st
Byte on the Network
2
nd
Byte on the Network
3
rd
Byte on the Network
4
th
Byte on the Network
5
th
Byte on the Network
6
th
Byte on the Network
A5h
See
A5h
See
See
8.4.1
EEPROM Loader Operation
Upon a pin reset (nRST), power-on reset (POR), digital reset (Digital
bit in the
or upon the issuance of a RELOAD command via the
the
bit in the
will be set. While the EEPROM Loader is active, the
bit of the
is cleared and no writes to the
device should be attempted. The operational flow of the EEPROM Loader can be seen in
SMSC LAN9303/LAN9303i
DATASHEET
113
Revision 1.3 (08-27-09)
SMSC [ SMSC CORPORATION ]
