Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
8.3.3
I
2
C EEPROM Sequential Byte Reads
Following the device addressing, data bytes may be read sequentially from the EEPROM by outputting
a start condition and control byte with a control code of 1010b, chip/block select bits as described in
and the R/~W bit high. The EEPROM will respond with an acknowledge, followed by 8-
bits of data. If the EEPROM slave fails to send an acknowledge, then the sequence is aborted and
the
bit in the
is set. The I
2
C master then sends an acknowledge, and the EEPROM responds with the
next 8-bits of data. This continues until the last desired byte is read, at which point the I
2
C master
sends a no-acknowledge, followed by a stop condition.
illustrates typical I
2
C EEPROM sequential byte reads for single and double byte addressing.
Control Byte
Data Byte
Data Byte
A
A
A
A
A
A A
D D D D D D D D
D D D D D D D D
C
S 1 0 1 0
1
C
C
1
C
K
0
9 8
K
7 6 5 4 3 2 1 0
K
7 6 5 4 3 2 1 0
K
...
Data Byte
D D D D D D D D
A
P
7 6 5 4 3 2 1 0
C
K
Chip / Block R/~W
Select Bits
Single Byte Addressing Sequential Reads
Control Byte
Data Byte
Data Byte
A
A
A
A
D D D D D D D D
D D D D D D D D
C
S 1 0 1 0 0 0 0 1
C
C
C
K
K
7 6 5 4 3 2 1 0
K
7 6 5 4 3 2 1 0
K
...
Data Byte
D D D D D D D D
A
P
7 6 5 4 3 2 1 0
C
K
Chip / Block R/~W
Select Bits
Double Byte Addressing Sequential Reads
Figure 8.4 I
2
C EEPROM Sequential Byte Reads
Sequential reads are used by the EEPROM Loader. Refer to
for
additional information.
For a register level description of a read operation, refer to
8.3.4
I
2
C EEPROM Byte Writes
Following the device addressing, a data byte may be written to the EEPROM by outputting the data
after receiving the acknowledge from the EEPROM. The data byte is acknowledged by the EEPROM
slave and the I
2
C master finishes the write cycle with a stop condition. If the EEPROM slave fails to
send an acknowledge, then the sequence is aborted and the
bit in the
is set.
Following the data byte write cycle, the I
2
C master will poll the EEPROM to determine when the byte
write is finished. After meeting the minimum bus free time, a start condition is sent followed by a control
byte with a control code of 1010b, chip/block select bits low, and the R/~W bit low. If the EEPROM is
finished with the byte write, it will respond with an acknowledge. Otherwise, it will respond with a no-
acknowledge and the I
2
C master will issue a stop and repeat the poll. If the acknowledge does not
occur within 30mS, a time-out occurs. The check for timeout is only performed following each no-
acknowledge, since it may be possible that the EEPROM write finished before the timeout but the
30mS expired before the poll was performed (due to the bus being used by another master).
Once the I
2
C master receives the acknowledge, it concludes by sending a start condition, followed by
a stop condition, which will place the EEPROM into standby.
SMSC LAN9303/LAN9303i
DATASHEET
109
Revision 1.3 (08-27-09)
SMSC [ SMSC CORPORATION ]
